1. Field of the Invention
This invention relates to an IC package in which either of an IC chip operated by a single power supply and an IC chip operated by multiple power supplies can be packaged, and also to a packaging method for the same.
2. Description of the Related Art
Recently, owing to improvements in the process and the circuit technology, an LSI, which is an IC having a larger number of circuit elements, can be constructed by forming CMOS (Complementary Metal-Oxide semiconductor) devices using PMOS FETs and NMOS FETs and bipolar transistors on a single chip, thereby allowing the LSI to perform various functions. For example, in a BiCMOS gate array described in NEC GIHO, 1990, Vol. 43, No. 12, pp. 119-121 and having logic circuits composed of CMOS devices and bipolar transistors, the function of the LSI can be enhanced by forming ECL (Emitter Coupled Logic) devices which can operate at a high speed on a single chip, in addition to conventional TTL (Transistor Transistor Logic) devices.
FIG. 1 shows the structure of an example of gate array which can interface with input and output levels of a TTL device. In the gate array of FIG. 1, a TTL input buffer 21 which transmits the input of a TTL device to the internal of an LSI, an internal gate 22 which constitute a logic using BiCMOS (or CMOS) devices, and a TTL output buffer 23 which receives a signal from the internal gate 22 and outputs it at the TTL level are connected in series. The TTL input buffer 21 is coupled to a TTL input terminal TI, and the TTL output buffer 23 to a TTL output terminal TO. The LSI chip is connected to a positive power supply terminal VCC and also to a ground terminal GND, and a positive voltage (usually, 5 V) is applied to the LSI chip. In the thus configured gate array, a single power supply voltage is applied to the IC chip.
FIG. 2 shows the structure of an example of gate array which can interface with input and output levels of a TTL device and ECL device. In FIG. 2, parts designated by the same reference numerals as FIG. 1 are identical with those of FIG. 1. In the figure, 24 designates an ECL input buffer which is coupled to an ECL input terminal EI and transmits the input of an ECL device to the internal of an LSI, and 25 designates an ECL output buffer which is coupled to an ECL outputs terminal EO, receives a signal from the internal gate 22 and outputs it at the ECL level. Level converters 26 and 27 which convert the TTL to the logic level of the internal gate 22 are connected to the TTL input buffer 21 and the TTL output buffer 23, respectively. The LSI chip is connected also to a negative power supply terminal VEE, in addition to the positive power supply terminal VCC and the ground terminal GND, so that a negative voltage (usually, -5 V or -4.5 V) is applied together with the positive voltage to the LSI chip. In the thus configured gate array, two kinds of power supply voltages (positive and negative voltages) are applied to the IC chip.
Both the configurations of FIGS. 1 and 2 can be obtained from the same master chip. In the field of gate arrays, generally, packages in which IC chips are to be packaged are common to all the IC chips. For example, it is known that an IC chip is packaged in a ceramic package which is made of fine ceramic, as shown in FIG. 3. FIG. 4 is a sectional view taken along the line IV--IV of FIG. 3.
In FIGS. 3 and 4, the numeral 1 designates a package body which is made of fine ceramic. On the surface of the package body 1, a ring-shaped metal wiring pattern 2 is formed. A lid 10 for sealing an IC chip 4 in the package is connected to the metal wiring pattern 2 by soldering or the like. In FIG. 3, the illustration of the lid 10 is omitted. In a die bonding region 6 which is the center region surrounded by the metal wiring pattern 2, the IC chip 4 having a number of pads 7 which are arranged in the periphery of the chip is bonded to the package body 1. A number of internal wiring electrodes 3 for the package are formed in the region between the metal wiring pattern 2 and the die bonding region 6, and connected with the corresponding pads 7 through wires 5, respectively. Many external leads 8 which respectively correspond to the positive power supply terminal VCC, the negative power supply terminal VEE, the ground terminal GND, etc. are drawn out from the package body 1. The connections between the external leads 8 for the positive power supply terminal VCC and ground terminal GND and the corresponding internal wiring electrodes 3, and between the external lead 8 for the negative power supply terminal VEE and the die bonding region 6 are performed by wirings 9 which are formed in the package body 1. In a package of a certain kind, generally, the power supply pins for the positive power supply terminal VCC, negative power supply terminal VEE and ground terminal GND are allocated to predetermined external lead positions.
When the package having the above-mentioned conventional structure is commonly used for packaging an IC chip with a single power supply such as shown in FIG. 1 and an IC chip with positive and negative power supplies, there arises the following inconvenience. In the case that the IC chip with a single power supply is packaged, the external lead 8 for the negative power supply terminal VEE is not used to become a useless lead. Moreover, the die bonding region 6, which is to be connected with the negative power supply terminal VEE in the case that the IC chip with positive and negative power supplies is packaged, must be connected with the ground terminal GND or the positive power supply terminal VCC so that the potential of the region is fixed. This requires a further wiring operation to be performed.
This inconvenience may be solved by separately preparing the package for the IC chip with a single power supply and that for the IC chip with positive and negative power supplies. However, this countermeasure poses a problem in that the packages to be prepared are so various that the cost for developing the packages becomes high.